This invention relates to an analog/digital conversion circuit, and more particularly to an improvement of a series parallel type analog/digital conversion circuit which,, converts analog signals into digital signals while separating the same into high order and low order signals.
A conventional analog/digital conversion circuit (hereinbelow called as an A/D conversion circuit) which converts analog signals such as video signals into digital data, for example, an A/D conversion circuit called a two step series parallel type, is proposed in Japanese Patent Application Laid Open Number 2-137420.
In FIG. 1, 1 shows the entirety of an A/D conversion circuit which separates a hold voltage VI obtained by sample-holding an input video signal VD into two steps of higher order bits and lower order bits and outputs four bit digital data D1, D2, D3 and D4.
In the A/D conversion circuit 1, a sample hold circuit 2 and reference voltage generating circuit 3 output the hold voltage VI, reference voltages VU1 to VU3 and VD1 to VD8 to a higher order comparing circuit unit 4 and a lower order comparing circuit unit 5.
The reference voltage generating circuit 3 is constituted by series connected sixteen resistors R1 to R16 between reference voltages VRT and VRB and twenty switching blocks SB12 to SB58 arranged in matrix form of 5 rows.times.8 columns as shown in FIG. 2.
The reference voltage generating circuit 3 is adapted to output the reference voltages VU1 to VU3, which are obtained by dividing the difference reference voltage VRT-VRB into four, to the higher order comparing circuit unit 4.
Further the reference voltage generating circuit 3 subdivides the difference reference voltages VRT-VU1 (VU1-VU2, VU2-VU3 and VU3-VRB) selected in the higher order comparing circuit unit 4 while incorporating its redundancy to obtain the reference voltages VD1 to VD8 and as well is adapted to output the hold voltage VI to the lower order comparing circuit unit 5 via lines L1A to L8B and output the reference voltages VD1-VD8 to the lower order comparing circuit unit 5 via lines L1B to L8B.
The higher order comparing circuit unit 4 includes three comparator arrangements 41 to 43, supplies the hold voltage VI to the non-inverted input terminals of respective comparators CU1 to CU3 in the comparator arrangements 41 to 43, and as well supplies the reference voltages VU1 to VU3 to the respective inverted terminals.
The higher order comparing circuit unit 4 compares these reference voltages VU1 to VU3 with the hold voltages VI, converts the comparison result into three sets of line signals SA, SB and SC via an encoder 6 constituted by wired OR circuits, and outputs the same to a selection circuit unit 7.
Herein the encoder 6, for example, outputs logic "0", 1" and "1" as the line signals SA, SB and SC when the output of an AND circuit AU1, and the selection circuit 7 outputs logic "0" or "1" in response to the output result of the selection signals XA, XB and XC.
Further, when the output of either of AND circuits AU2 to AU4 is logic "1" the selection circuit unit 7 outputs logic "0" or "1" in response to the output result of the selection signals XA, XB and XC thereby enabling correction of the detection result in the higher order comparing circuit unit 4.
Further, the higher order comparing circuit unit 4 outputs reference voltage control signals X1 to X4 of the comparator arrangements 41 to 43 to the reference voltage generating circuit 3 and causes the same to output the reference voltages VD1 to VD8 in response to the detection result to the lower order comparing circuit unit 5.
The lower order comparing circuit unit 5 as shown in FIG. 3 includes eight comparator arrangements 51 to 58, supplies the hold voltage VI to the non-inverted input terminals of the respective comparators CD1 to CD8 in the comparator arrangements 51 to 58, and as well is adapted to supply the lower order bit comparing reference voltages VD1 to VD8 to the inverted input terminals.
The lower order comparing circuit unit 5 compares the reference voltages VD1 to VD8 with the hold voltage VI and outputs the result of the comparison, and the encoder 8 converts the comparison result into code data and outputs the least significant bit D2 in higher order converted data and lower bits D3 and D4 in lower order converted data and as well outputs selection signals XA, XB and XC to the selection circuit unit 7.
The selection circuit unit 7 as shown in FIG. 5 is composed of an AND - OR circuit formed by transistors wherein three outputs from three sets of AND circuits having two input terminals are output via a three input OR circuit thereby when either of the selection signals XA, XB and XC is an "H" level signal (being a higher potential) one of the line signals SA, SB and SC is selected and is output as the most significant bit D1.
Namely, in the selection circuit unit 7, the AND circuits are formed by sets of transistors (Q1A and/or Q2A, Q3A), (Q1B and/or Q2B, Q3B) and (Q1C and/or Q2C, Q3C), the inverted output of the most significant bit D1 is obtained via a resistor R1 and as well the non-inverted output of the most significant bit D1 is obtained via a resistor R2.
Thereby, the selection circuit unit 7 operates to correct the code data of the most significant bit D1 when the video signal VD is in the vicinity of the quantization level of two higher order bits, for instance, the video signal VD is near the level of the higher order bit comparing reference voltages VU1, VU2 and VU3.
As shown in FIG. 6, a video signal is detected by the higher order comparing circuit unit 4 as a value of the second difference potential VU1-VU2 from the highest order, due to the overshooting of the sample hold circuit 2 and a logic "1" is output as the value of the most significant bit D1 at the time when the true converted value of the video signal VD into digital data D1, D2, D3 and D4 is "0111". If the value "111" is obtained as the second bit D2 and lower order bits D3 and D4 from the lower redundant bits, the selection circuit unit 7 outputs the output of the higher order conversion code data SC, in that logic "1" for the significant bit D1, out of the higher order conversion code data SA, SB and SC because only the selection signal XC is in "H" level. As a result, the output is corrected to "0111".
However, more than two signals of the selection signals XA, XB and XC can be rendered at an "H" level because of output error from the lower order comparing circuit unit 5, and an incorrect higher order bit D1 is possibly selected such that there arised a problem that a small error in the lower order comparing circuit unit 5 causes a large error in a higher order bit.
For instance in connection with the above occurrence when both outputs of the signals XA and XC are incidentally rendered to an "H" level, the selection circuit unit 7 outputs the line signal SA or SC, in that outputs logic "1" as the most significant bit D1 as a result "1111" is output as the digital data after A/D conversion. Therefore there arises a possibility that the correction based upon the lower order bits likely causes a large error.